Conventional scaling of the Si MOSFET into the deep submicron regime requires high substrate doping levels. This extracts a severe speed penalty, if lower standby power consumption (i.e., good subthreshold behavior) is to be maintained. We explore the scaling of fully depleted silicon‐on‐insulator (SOI) structures, and show, both analytically and by numerical simulation, how the horizontal leakage is controlled by vertical doping engineering. Our analysis allows different structures to be evaluated in terms of a natural length scale indicating good subthreshold behavior. Finally, we describe how retrograde doping may be used to mimic the SOI concept in bulk Si. Our results show good subthreshold behavior in the deep submicron regime can be achieved without large junction capacitance, high threshold voltage, or heavy channel doping.