Polycrystalline silicon (poly) gate metal‐oxide‐semiconductor (MOS) transistors were electrically stressed by constant‐current tunneling. After the stress the devices were thermally annealed for variable times in the temperature range between 800 and 950 °C, and a second tunneling stress was performed. Capacitance‐voltage (C‐V) curve broadening and a charge pumping (CP) technique were used to detect interface state generation. It was found that the stress generated interface states are totally annealed by the thermal treatment. On the other hand, generation rates and saturation values, due to the second stress after annealing, exceed those of the fresh devices. Analysis of the generation process indicates that two types of interface states are generated: one, similar in its generation rate and saturation value to that of a fresh device, and another one, which is characterized by a higher generation rate and saturation value, is attributed to a new type of latent site. The density of this new type of latent interface states site decays exponentially with the annealing time. The annealing rate follows a temperature‐dependent Arrhenius function. The anneal of this new type of interface state is characterized by an activation energy of 3.47 eV.