We present the results of numerical simulations of a functionally complete set of complementary logic circuits based on capacitively coupled single‐electron transistors (CSETs). The family includes an inverter/buffer stage, as well as two‐input NOR, NAND, and XOR gates, all using similar tunnel junctions, and the same dc bias voltage and logic levels. Maximum operation temperature, switching speed, power consumption, noise tolerances, error rate, and critical parameter margins of the basic gates have been estimated. When combined with the data from a preliminary geometrical analysis, the results indicate that implementation of the CSET logic family for operation at T∼20 K will require fabrication of structures with ∼2‐nm‐wide islands separated by ∼1‐nm‐wide tunnel gaps. © 1996 American Institute of Physics.