APL Nameplate
  • Volume/Page
  • Keyword
  • DOI
  • Citation
  • Advanced
   
 
 
 

Flickr Twitter iResearch App Facebook

BROWSE VOLUMES

Year Range: 
Search Issue | RSS Feeds RSS
Previous Issue Next Issue

23 Aug 1999

Volume 75, Issue 8, pp. 1033-1181

Return to All Sections
back to top
RSS Feeds

Thin gate oxide behavior during plasma patterning of silicon gates

L. Vallier, L. Desvoivres, M. Bonvalot, and O. Joubert

Appl. Phys. Lett. 75, 1069 (1999); http://dx.doi.org/10.1063/1.124599 (2 pages) | Cited 15 times

Full Text: Read Online (HTML) | Download PDF

Show Abstract
We have evidenced an unexpected behavior of thin gate oxide layers (thickness in the range 2–4 nm) exposed to plasma processes developed for the patterning of 0.1 μm silicon gates. During the low-energy overetch step of the process, an oxidation of the bulk underlying silicon takes place, leading to the growth of the gate oxide layer. Experimental results obtained from in situ kinetic and spectroscopic ellipsometry measurements and supported by x-ray photoelectron spectroscopy analyses are presented to highlight this phenomenon. © 1999 American Institute of Physics.
Show PACS
81.65.Cf Surface cleaning, etching, patterning
52.77.Bn Etching and cleaning
52.77.Dq Plasma-based ion implantation and deposition
81.05.Cy Elemental semiconductors
82.80.Pv Electron spectroscopy (X-ray photoelectron (XPS), Auger electron spectroscopy (AES), etc.)
81.65.Mq Oxidation
Return to All Sections
Close

Google Calendar

ADVERTISEMENT

Go to AIP Home   © AIP Publishing LLC
close