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10 May 2004

Volume 84, Issue 19, pp. 3723-3937

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Appl. Phys. Lett. 84, 3933 (2004); http://dx.doi.org/10.1063/1.1745103 (3 pages)

A. Cassinese, G. M. De Luca, A. Prigiobbo, M. Salluzzo, and R. Vaglio
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Toward improved and tunable polymer field-effect transistors

Ludvig Edman, James Swensen, Daniel Moses, and Alan J. Heeger

Appl. Phys. Lett. 84, 3744 (2004); http://dx.doi.org/10.1063/1.1737483 (3 pages) | Cited 14 times

Online Publication Date: 29 April 2004

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We report an electrochemical method to improve charge injection in thin-film field-effect transistors fabricated with semiconducting polymers. By having ions, which are mobile only at elevated temperatures, in the active material [a mixture of a soluble poly(para-phenylene vinylene) copolymer, a crown ether and a LiCF3SO3 salt] we create electric double layers at the drain/source Au electrode interfaces by applying a low voltage (V = 2 V) at T = 85 °C for a short time (t ∼ 1–5 min). After cooling to room temperature under applied voltage, we demonstrate significantly improved transistor performance. In addition, we present evidence of reversible electrochemical doping in this active material. © 2004 American Institute of Physics.
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85.30.Tv Field effect devices

High mobility of pentacene field-effect transistors with polyimide gate dielectric layers

Yusaku Kato, Shingo Iba, Ryohei Teramoto, Tsuyoshi Sekitani, Takao Someya, Hiroshi Kawaguchi, and Takayasu Sakurai

Appl. Phys. Lett. 84, 3789 (2004); http://dx.doi.org/10.1063/1.1739508 (3 pages) | Cited 80 times

Online Publication Date: 29 April 2004

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Polyimide gate dielectric layers cured at 180 °C have been employed to fabricate high-quality pentacene field-effect transistors on polyethylenenaphthalate-based films. The surface roughness (root-mean square) of gate dielectric layers characterized by atomic force microscopy is only 0.2 nm, while that of the base film is 1 nm. The transistors with pentacene channel layers deposited on 990 nm polyimide gate dielectric layers attain the on/off ratio of 106 and mobility of 0.3 cm2/V s. Furthermore, by decreasing the thickness of polyimide gate dielectric layers down to 540 nm, the mobility is enhanced up to 1 cm2/V s. © 2004 American Institute of Physics.
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85.30.Tv Field effect devices
73.61.Ph Polymers; organic compounds
77.55.-g Dielectric thin films
68.37.Ps Atomic force microscopy (AFM)
73.50.Dn Low-field transport and mobility; piezoresistance
85.65.+h Molecular electronic devices

High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure

Yung-Chun Wu, Ting-Chang Chang, Chun-Yen Chang, Chi-Shen Chen, Chun-Hao Tu, Po-Tsun Liu, Hsiao-Wen Zan, and Ya-Hsiang Tai

Appl. Phys. Lett. 84, 3822 (2004); http://dx.doi.org/10.1063/1.1745104 (3 pages) | Cited 13 times

Online Publication Date: 29 April 2004

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This investigation examines polycrystalline silicon thin-film transistors (TFTs) with multiple nanowire channels and a lightly doped drain (LDD). A device with an LDD structure exhibits low leakage current because the lateral electrical field is reduced in the drain offset region. Additionally, multiple nanowire channels can generate fewer defects in the polysilicon grain boundary and have more efficient NH3 plasma passivation than single-channel TFTs, further reducing leakage current. They exhibit superior electrical characteristics to those of single-channel TFTs, such as a higher ON/OFF current ratio (>108), a better subthreshold slope of 110 mV/decade, an absence of drain-induced barrier lowering, and suppressed kink-effect. Devices with the proposed TFTs are highly promising for use in active-matrix liquid-crystal display technologies. © 2004 American Institute of Physics.
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85.30.Tv Field effect devices
81.05.Cy Elemental semiconductors
81.65.Rv Passivation
61.72.Mm Grain and twin boundaries

A polymer blend approach to fabricating the hole transport layer for polymer light-emitting diodes

He Yan, Qinglan Huang, Brian J. Scott, and Tobin J. Marks

Appl. Phys. Lett. 84, 3873 (2004); http://dx.doi.org/10.1063/1.1737791 (3 pages) | Cited 19 times

Online Publication Date: 29 April 2004

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This contribution describes an approach to fabricating high-efficiency hole-transport layers (HTLs) for polymer light-emitting diodes (PLEDs). HTLs fabricated by this approach have two components: a siloxane-derivatized, crosslinkable, hole-transporting material and a hole-transporting polymer. These HTLs exhibit high transparency, have no corrosive effects on the indium tin oxide anode, and have minimal pixel “cross-talk” potential. PLEDs that are fabricated using these HTLs exhibit superior performance (40% greater maximum current efficiency) versus analogous devices using a conventional poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT-PSS) HTL. Most importantly, this approach has considerable flexibility and can be applied as a general strategy to manipulate energy level alignments in PLEDs. © 2004 American Institute of Physics.
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85.60.Jb Light-emitting devices
42.70.Jk Polymers and organics
42.86.+b Optical workshop techniques
72.20.Fr Low-field transport and mobility; piezoresistance
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