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Applied Physics Letters / Volume 88 / Issue 10 / ELECTRONIC TRANSPORT AND SEMICONDUCTORS

Appl. Phys. Lett. 88, 102105 (2006); http://dx.doi.org/10.1063/1.2182070 (3 pages)

Random telegraph signal in nanoscale back-side charge trapping memories

H. Silva and S. Tiwari

School of Applied and Engineering Physics, Cornell University, Ithaca, New York 14853

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(Received 12 May 2005; accepted 22 January 2006; published online 9 March 2006)

Random telegraph signal (RTS) was observed in the front and back channel source-drain current of nanoscale double-gated back-side charge trapping memories. The front gate dielectric is silicon oxide and the back gate dielectric is a stack of silicon oxide–silicon nitride–silicon oxide (ONO). The structure provides a tool for traps characterization at multiple interfaces and combinations of materials. Bias dependence of RTS due to a trap in the back ONO was measured to determine the position of the trap in the dielectric. The results show that the individual trap is located within the tunneling oxide, 1.3 nm away from the silicon interface. RTS due to traps responsible for the memory properties, located in the silicon nitride or its interface, was not observed.

© 2006 American Institute of Physics

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KEYWORDS and PACS

Keywords

silicon compounds, nanostructured materials, electron traps, hole traps, semiconductor storage

PACS

ARTICLE DATA

Digital Object Identifier
http://dx.doi.org/10.1063/1.2182070

PUBLICATION DATA

ISSN

0003-6951 (print)  
1077-3118 (online)

Publisher

$abstract.society.value is a Member of CrossRef American Institute of Physics

For access to fully linked references, you need to log in.
    K. S. Ralls, W. J. Skocpol, L. D. Jackel, R. E. Howard, L. A. Fetter, R. W. Epworth, and D. M. Tennant, Phys. Rev. Lett. 52, 228 (1984).


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