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Applied Physics Letters / Volume 96 / Issue 26 / DEVICE PHYSICS

Appl. Phys. Lett. 96, 263501 (2010); http://dx.doi.org/10.1063/1.3457446 (3 pages)

Self-aligned imprint lithography for top-gate amorphous silicon thin-film transistor fabrication

E. Lausecker1,2, Y. Huang1, T. Fromherz2, J. C. Sturm1, and S. Wagner1

1Department of Electrical Engineering, Princeton Institute for the Science and Technology of Materials (PRISM), Princeton University, Princeton, New Jersey 08544, USA
2Institute of Semiconductor and Solid State Physics, Johannes Kepler University Linz, 4040 Linz, Austria

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(Received 12 February 2010; accepted 3 June 2010; published online 28 June 2010)

We developed self-aligned imprint lithography (SAIL) for top-gate amorphous silicon (a-Si) thin-film transistors (TFTs). Our SAIL process enables a device pattern definition in a single imprint step that uses a three-level mold. The various levels of the mold are defined by a stepwise opening of a chromium hardmask and subsequent dry-etching. For TFT fabrication we imprint, and consecutively etch the imprint resist levels and device layers. The imprinted top-gate a-Si TFTs have nickel silicide source/drain self-aligned to the gate with mobilities of ∼ 0.4 cm2/V s.

© 2010 American Institute of Physics

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KEYWORDS and PACS

Keywords

amorphous semiconductors, elemental semiconductors, etching, masks, nanolithography, resists, silicon, thin film transistors

PACS

ARTICLE DATA

Digital Object Identifier
http://dx.doi.org/10.1063/1.3457446

PUBLICATION DATA

ISSN

0003-6951 (print)  
1077-3118 (online)

Publisher

$abstract.society.value is a Member of CrossRef American Institute of Physics

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    D. Y. Choi, J. H. Lee, D. S. Kim, and S. T. Jung, J. Appl. Phys. 95, 8400 (2004)JAPIAU000095000012008400000001.


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